NXP Semiconductors /LPC15xx /DMA /INTENCLR0

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Interpret as INTENCLR0

Description

Interrupt Enable Clear for all DMA channels.

Fields

CLR0	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR1	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR2	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR3	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR4	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR5	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR6	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR7	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR8	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR9	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR10	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR11	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR12	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR13	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR14	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR15	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR16	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
CLR17	Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
RESERVED	Reserved.

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